Language Breakdown
Lines of code distribution across 9 owned repositories
T-Shaped Developer
T-shapedDeep in SystemVerilog with broad versatility
Collaboration Network
Global Impact visualization
Repos
227
PRs
0
Growth
+18%
Top Collaborators
No collaborator data yet.
Coding Streak
Contribution activity over the past year
Top Repositories
AHBLite bus to APB4 bridge
DDR3 Controller v1.50, 16 read/write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. HDMI video controller included.
A SystemVerilog UVM-based I2C Verification IP (VIP) designed to verify I2C slave/master implementations. The environment includes configurable driver, monitor, sequencer, sequences, and scoreboard supporting read/write transactions, repeated-start handling and functional coverage.
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs
round robin arbiter
Full Speed USB interface for FPGA and ASIC designs
Source code repo for UVM Tutorial for Candy Lovers
General Purpose AXI Direct Memory Access
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
Open Source Impact
Contributions to external projects
No external contributions found.